1. Field of the Invention
The present invention relates to a data processor, and more specifically to a data processor including a plurality of general register sets (called "register banks" hereinafter) used for data processing and operating to designate a predetermined register bank in response to an interrupt acknowledge signal responding to an interrupt request signal, and thereafter to execute an interrupt handling program.
2. Description of Related Art
Conventional microcomputer systems have included an interrupt controller, so that when an interrupt request signal is generated by a peripheral device during execution of a main program, a central processing unit (called "CPU" hereinafter) can interrupt the execution of the main program and then execute an interrupt handling program corresponding to the interrupt request signal generated by the peripheral device. If a number of peripheral devices are provided, a plurality of interrupt request signals can be concurrently or simultaneously generated in one case. On the other hand, in another case, when an interrupt handling program for an interrupt request signal from one peripheral device is under execution, another interrupt request signal can be generated by another peripheral device. In order to deal with the above mentioned conflict of a plurality of interrupt request signals, a priority level control has been needed, in which different priority levels are assigned to respective interrupt request signals, so that a handling program corresponding to an interrupt request signal having a high priority level is preferentially executed.
In general, a vector interrupt system and a register bank switching system have been known as interrupt processing systems for the microcomputer system. In the vector interrupt system, when an interrupt request signal is acknowledged, the contents of a program counter which designates an address of a main program under execution, and the contents of a program status word storing the status of the execution of the main program are saved in a memory stack. On the other hand, an interrupt code is generated in correspondence to the acknowledged interrupt request signal, and thereafter, a start address (called "vector address" hereinafter) of a handling program corresponding to the acknowledged interrupt request signal is produced on the basis of the generated interrupt code, and is set into the program counter, so that the interrupt handling program is executed. In the process of execution of the interrupt handling program, the contents of a general register are saved in the memory stack, similarly to the program counter and the program status word.
In this vector interrupt system, one interrupt code is determined for each of the interrupt requests, and therefore, a start address for an interrupt handling program is also determined for each of interrupt requests, so that the interrupt handling program corresponding to each give interrupt request can be started.
On the other hand, in the register bank switching system, a plurality of register banks are provided, and one of the plurality of register banks is selected in response to an interrupt request acknowledge signal, so that a branch is executed on the basis of the contents of the selected register bank.
More specifically, when an interrupt request signal is acknowledged, a register bank designation code is generated in correspondence to the acknowledged interrupt request signal, and set into a register bank designation register so as to designate a predetermined register bank within a data memory. As a result, the register bank to be accessed by the CPU is switched to the predetermined register bank corresponding to the given interrupt request signal. Each of the register banks includes a number of general registers, a program counter save area, a program status word save area, etc, and stores a start address of an interrupt handling program at a last portion of the register bank. Therefore, the CPU operates to save the contents of the program counter and the program status word in the program counter save area and the program status word save area of the newly selected register bank, and the start address of an interrupt handling program (namely, a new program counter value) stored in the newly selected register bank is set into the program counter, so that the interrupt handling program corresponding to each given interrupt request can be started.
In the above mentioned vector interrupt system, a great deal of time is required for processing, saving and returning to the general registers contents executed in the interrupt handling program, and therefore, operation efficiency of interrupt processing is very low. In the above mentioned register bank switching system, on the other hand, since it is not necessary to save and return contents of the general registers, operation efficiency is excellent as compared with that of the vector interrupt system. However, with an increase in functions performed by microcomputer systems, the microcomputer systems are apt to have an increased number of peripheral devices, and therefore, the number of interrupt requests generated by the peripheral devices have increased. But, it is practically or physically impossible to provide the microcomputer system with one individual register bank for each one of a number of interrupt requests, since a large memory capacity would have to be provided in the microcomputer system.
In order to avoid the number of interrupts designated in the register bank interrupt system from being limited by the number of register banks, it has been proposed to arrange interrupt requests into a limited number of groups and provide one register bank for each of the interrupt request groups. In this case, however, since interrupt processing is executed by using one register bank common to all the interrupts included in one interrupt request group, the start addresses for respective interrupt handling programs for respective interrupts included in one interrupt request group are the same. Therefore, during execution of an interrupt handling program, it is not possible to know by which of interrupt request sources in a selected interrupt request group an interrupt is triggered. As a result, only one interrupt request within each interrupt request group can be dealt with in the register bank switching system, while the other interrupt requests within each interrupt request group must be dealt with in the vector interrupt system.